By Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
This ebook discusses the layout and function research of SDRAM controllers that cater to either real-time and best-effort purposes, i.e. mixed-time-criticality reminiscence controllers. The authors describe the state-of-the-art, after which specialize in an structure template for reconfigurable reminiscence controllers that addresses successfully the speedy evolving set of SDRAM criteria, by way of worst-case timing and gear research, in addition to implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA improvement board are used as an evidence of inspiration of the structure template.